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AXI

When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For this reason protocols need to be established, such as letting others speak without interruption, or facing those you are addressing. The same is necessary with electronics, especially with system on chip (SoC) designs.


Introducing the AXI Protocol

The protocol used by many SoC designers today is AXI, or Advanced eXtensible Interface, and is part of the Arm Advanced Microcontroller Bus Architecture (AMBA) specification. It is especially prevalent in Xilinx’s Zynq devices, providing the interface between the processing system and programmable logic sections of the chip.My first introduction with the interface was in a tutorial I was following that was to be implemented on Aldec’s own development board based off the Zynq XC7Z030, the TySOM™ board. (The TySOM™ Embedded Development Kit is for the embedded designers who need a high-performance RTL simulator/debugger for their embedded applications such as IoT, Automotive, Factory automation, UAV and Robotics. The kit includes Riviera-PRO™ Advanced Verification Platform and a TySOM development/prototyping board. TySOM boards come with either a Zynq 7000 chip (FPGA + Dual ARM® Cortex™-A9) or with a Zynq® UltraScale+™ MPSoC device. These boards include memories, and various communication and multimedia interfaces in addition to FMC connectors for peripheral expansion).
High-pin count (HPC), 400 I/O FPGA Mezzanine Card (FMC) connectors
Top: mezzanine card side
Bottom: baseboard side
FPGA Mezzanine Card (FMC) is an ANSI/VITA (VMEbus International Trade Association) 57.1 standard that defines I/O mezzanine modules with connection to an FPGA or other device with re-configurable I/O capability.[1][2] It specifies a low profile connector and compact board size for compatibility with several industry standardslot card, blade, low profile motherboard, and mezzanine form factors.
The FMC specification defines:[3]
  • I/O mezzanine modules, which connect to carrier cards
  • A high-speed connector family of connectors for I/O mezzanine modules
    • Supporting up to 10 Gbit/s transmission with adaptively equalized I/O
    • Supporting single ended and differential signaling up to 2 Gbit/s
    • Numerous I/O available
  • The electrical connectivity of the I/O mezzanine module high-speed connector
    • Supporting a wide range of signaling standards
    • System configurable I/O functionality
    • FPGA intimacy
  • The mechanical properties of the I/O mezzanine module
    • Minimal size
    • Scalable from low end to high performance applications
    • Conduction and ruggedized support

The FMC specification has two defined sizes: single width (69 mm) and double width (139 mm). The depth of both is about 76.5 mm.[4] The FMC mezzanine module uses a high-pin count 400 pin high-speed array connector. A mechanically compatible low pin count connector with 160 pins can also be used with any of the form factors in the standard.
The project utilized several of the board’s peripheral connections including HDMI, touchscreen, LEDs, and switches. Despite the various types of inputs and outputs, the IP cores all shared a common interface: AXI. Knowing the differences between these devices, I was interested in why each IP Core was able to share this common interface. Reading more into the technology I found out just why AXI has become the most widespread AMBA interface.
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How AXI became the most widespread AMBA interface

The protocol simply sets up the rules for how different modules on a chip communicate with each other, requiring a handshake-like procedure before all transmissions. Having a protocol such as this allows a true “system” rather than a “collection” of modules to be established as the protocol connects and provides an effective medium for transfer of data between the existing components on the chip

Protocol specifications

The specifications of the protocol are quite simple, and are summarized below:
  • Before transmission of any control signal/address/data, both master and slave must extend their “hand” for a handshake via ready and valid signals.
  • Separate phases exist for transmission of control signal/address and data.
  • Separate channels exist for transmission of control signal/address and data.
    • Burst type communication allows for continuous transfer of data.
To go more in depth, the interface works by establishing communication between master and slave devices. Between these two devices (or more if using an AXI Interconnect Core IP) exists five separate channels: Read Address, Write Address, Read Data, Write Data, and Write Response. Each channel has its own unique signals as well as similar signals existing among all five. The valid and ready signals exist for each channel as they allow for the handshake process to occur for each channel. For transmitting any signal (address/data/response/etc) the relevant channel source provides an active valid signal and the same channel’s destination must provide an active ready signal. After both signals are active, transmission may occur on that channel. As stated above, the transmission of control signals/address and data are done in separate phases, and therefore an address must always be transferred between devices before the handshake process can occur for the corresponding data transfer. In the case of writing information, the response channel is used at the completion of the data transfer.

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